| /XiangShan/src/main/scala/xiangshan/backend/fu/ |
| H A D | FuncUnit.scala | 80 val debug_seqNum = InstSeqNum() constant
87 val debug_seqNum = InstSeqNum() constant
108 …PerfCCT.updateInstPos(io.in.bits.debug_seqNum, PerfCCT.InstPos.AtFU.id.U, io.in.valid, clock, rese…
109 …PerfCCT.updateInstPos(io.out.bits.debug_seqNum, PerfCCT.InstPos.AtBypassVal.id.U, io.out.valid, cl…
126 io.out.bits.debug_seqNum := RegEnable(io.in.bits.debug_seqNum, io.in.fire)
142 io.out.bits.debug_seqNum := DataHoldBypass(io.in.bits.debug_seqNum, io.in.fire)
158 io.out.bits.debug_seqNum := io.in.bits.debug_seqNum
178 … val seqNumVec = init.debug_seqNum +: Seq.fill(latency)(Reg(chiselTypeOf(io.in.bits.debug_seqNum)))
199 case(((ctrl,data), perf), debug_seqNum) => {
207 out.debug_seqNum := debug_seqNum
[all …]
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| H A D | Fence.scala | 91 io.out.bits.debug_seqNum := io.in.bits.debug_seqNum
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| /XiangShan/src/main/scala/xiangshan/backend/ |
| H A D | Bundles.scala | 56 val debug_seqNum = InstSeqNum() constant
71 this.debug_seqNum := source.debug_seqNum
124 val debug_seqNum = InstSeqNum() constant
234 val debug_seqNum = InstSeqNum() constant
652 val debug_seqNum = InstSeqNum() constant
666 this.debug_seqNum := source.common.debug_seqNum
737 val debug_seqNum = InstSeqNum() constant
758 val debug_seqNum = InstSeqNum() constant
780 this.debug_seqNum := source.debug_seqNum
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| H A D | Backend.scala | 684 sink.bits.debug_seqNum := source.bits.uop.debug_seqNum
816 sink.bits.uop.debug_seqNum := source.bits.debug_seqNum
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| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | IBuffer.scala | 63 val debug_seqNum = InstSeqNum() constant
81 debug_seqNum := fetch.debug_seqNum(i)
108 cf.debug_seqNum := debug_seqNum
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| H A D | IFU.scala | 964 io.toIbuffer.bits.debug_seqNum.zipWithIndex.foreach { case (a, i) =>
968 io.toIbuffer.bits.debug_seqNum.zipWithIndex.foreach { case (a, i) =>
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| H A D | FrontendBundle.scala | 253 val debug_seqNum = Vec(PredictWidth, InstSeqNum()) constant
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| /XiangShan/src/main/scala/xiangshan/backend/exu/ |
| H A D | ExeUnit.scala | 270 sink.bits.debug_seqNum := source.bits.debug_seqNum
409 io.out.bits.debug_seqNum := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.debug_seqNum))
456 fu.io.in.bits.debug_seqNum := io.in.bits.uop.debug_seqNum
469 io.out.bits.uop.debug_seqNum := fu.io.out.bits.debug_seqNum
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| /XiangShan/src/main/scala/xiangshan/backend/decode/ |
| H A D | DecodeStage.scala | 89 PerfCCT.updateInstPos(d.bits.debug_seqNum, PerfCCT.InstPos.AtDecode.id.U, d.valid, clock, reset)
248 inst.bits.debug_seqNum := 0.U
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| /XiangShan/src/main/scala/xiangshan/backend/rename/ |
| H A D | Rename.scala | 99 PerfCCT.updateInstPos(o.bits.debug_seqNum, PerfCCT.InstPos.AtRename.id.U, o.valid, clock, reset)
283 o.bits.debug_seqNum := io.in(i).bits.debug_seqNum
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| /XiangShan/src/main/scala/xiangshan/mem/pipeline/ |
| H A D | AtomicsUnit.scala | 63 …PerfCCT.updateInstPos(io.in.bits.uop.debug_seqNum, PerfCCT.InstPos.AtFU.id.U, io.in.valid, clock, …
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| H A D | StoreUnit.scala | 77 …PerfCCT.updateInstPos(io.stin.bits.uop.debug_seqNum, PerfCCT.InstPos.AtFU.id.U, io.stin.valid, clo…
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| H A D | HybridUnit.scala | 162 …PerfCCT.updateInstPos(io.lsin.bits.uop.debug_seqNum, PerfCCT.InstPos.AtFU.id.U, io.lsin.valid, clo…
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| H A D | LoadUnit.scala | 215 …PerfCCT.updateInstPos(io.ldin.bits.uop.debug_seqNum, PerfCCT.InstPos.AtFU.id.U, io.ldin.valid, clo…
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| /XiangShan/src/main/scala/xiangshan/backend/issue/ |
| H A D | IssueQueue.scala | 118 …PerfCCT.updateInstPos(enq.bits.debug_seqNum, PerfCCT.InstPos.AtIssueQue.id.U, enq.valid, clock, re…
803 deq.bits.common.debug_seqNum := deqEntryVec(i).bits.payload.debug_seqNum
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| /XiangShan/src/main/scala/xiangshan/backend/datapath/ |
| H A D | DataPath.scala | 588 …PerfCCT.updateInstPos(s0.bits.common.debug_seqNum, PerfCCT.InstPos.AtIssueArb.id.U, s0.valid, cloc…
589 …PerfCCT.updateInstPos(s1_data.debug_seqNum, PerfCCT.InstPos.AtIssueReadReg.id.U, s1_valid, clock, …
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| /XiangShan/src/main/scala/xiangshan/ |
| H A D | Bundle.scala | 167 val debug_seqNum = InstSeqNum() constant
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| /XiangShan/src/main/scala/xiangshan/mem/lsqueue/ |
| H A D | StoreQueue.scala | 524 uop(stWbIndex).debug_seqNum := io.storeAddrIn(i).bits.uop.debug_seqNum
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| /XiangShan/src/main/scala/xiangshan/backend/rob/ |
| H A D | Rob.scala | 148 …PerfCCT.updateInstPos(wb.bits.debug_seqNum, PerfCCT.InstPos.AtWriteVal.id.U, wb.valid, clock, rese…
775 …PerfCCT.commitInstMeta(i.U, deqDebugInst.debug_seqNum, deqDebugInst.instrSize, io.commits.isCommit…
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| /XiangShan/src/main/scala/xiangshan/mem/ |
| H A D | MemBlock.scala | 377 …PerfCCT.updateInstPos(wb.bits.uop.debug_seqNum, PerfCCT.InstPos.AtBypassVal.id.U, wb.valid, clock,…
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